1. Field of the Invention
The invention relates to a method of fabricating a metal interconnect, and more particularly to a method of dual damascene process by using a hard mask.
2. Description of the Related Art
In many highly integrated semiconductor devices, more than two levels of interconnecting metal layers are called multilevel interconnects. The formation of multilevel interconnects are to support the three dimensional wiring line structure required by high density of devices. In the process of fabricating multilevel interconnects, a first level, or a lower level of metal wiring and interconnect are formed first, and a second metal wiring is formed afterwards to connect the first metal wiring and the interconnect. The first metal wiring includes a poly-silicon layer or a metal layer, which electrically connects the source/drain region of device formed in the substrate. The electrical connection between the substrate and the device in the substrate is performed by a via or a contact. Electrical connections between devices are performed by a second or a higher layer of metal wiring.
A dual damascene process is intensively developed to provide a more stable and more advanced method of fabricating interconnects in an integrated circuit (IC). By using chemical-mechanical polishing process (CMP) during dual damascene process, a greater variety of metals such as aluminum, copper and aluminum alloy can be selected without being restricted by the conventional etching process. Selecting from a greater variety of metals is advantageous to the requirement of a low resistance interconnects, and is also advantageous to prevent electromigration. Therefore, dual damascene process will be broadly applied in the fabrication process of very large semiconductor integration (VLSI) interconnects under 0.25 .mu.m technology.
In FIG. 1A to FIG. 1C, a conventional dual damascene process is shown. Referring to FIG. 1A, on a semiconductor substrate 10 comprising a metal wiring 11, a dielectric layer 12 such as a silicon oxide layer having a thickness of about 10000 .ANG. to 17000 .ANG. is formed, for example, by chemical vapour deposition (CVD). Using a first step of photolithography and etching with the etching time controlled, a metal trench 13 and 14 are formed within the dielectric layer 12. The etching time is controlled to define the depth of the predetermined second metal trench. However, the uniformity of trench depth across all wafer is difficult to control. Also, a ragged and uneven surface 15 is easily formed on the bottom of the metal trench 13 and 14 due to plasma etch.
Referring to FIG. 1B, a second step of photolithography and etching is performed. The contact window 16 is further etched to expose the metal wiring 11 therewithin.
Referring to FIG. 1C, the metal trench 13, 14 and the contact window 16 are filled with a conductive material. A glue layer is formed over the substrate 10 before the formation of the conductive material. Using CVD, the conductive material is then formed on the glue layer and fills the metal trench 13, 14 and the contact window 16. The unwanted part of the conductive layer is removed either by etching back or polishing. A second metal wiring, that is, 13a and 14a, are formed. The second metal wiring 14a is coupled with the metal wiring 11 by the contact 16.
In the above dual damascene, during the second step of photolithography and etching, a ragged and uneven surface is easily formed on surface of the bottom of the metal trench. The resolution of photolithography is seriously degraded.
To improve the resolution of photolithography and control the metal trench depth in the above process, another dual damascene process is disclosed. Referring to FIG. 2A, on a semiconductor substrate 20 comprising a metal wiring 21, a first dielectric layer 22 having a thickness of about 5000 .ANG. to 10000 .ANG. is formed. A thin silicon nitride layer 23 is then formed on the first dielectric layer 22 to serve as a stop layer for the subsequent etching process. The silicon nitride layer 23 is defined to form a contact window 24 which is formed in alignment with and on top of the metal wiring 21.
Referring to FIG. 2B, a second dielectric layer 25 is formed on the silicon nitride layer 23. A preferable second dielectric layer 25 includes a silicon oxide layer, and has a different etching rate with the silicon nitride layer 23. The second dielectric layer 25 has a thickness of about 5000 .ANG. to 8000 .ANG., the same as the thickness of the predetermined second metal wiring.
Referring to FIG. 2C, using photolithography and etching process, the contact window 26 and metal trenches 27, 28 are formed within the second dielectric layer 25. Within the metal trenches 27 and 28, with the silicon nitride layer 23 as a stop layer, the etching process is stopped thereupon.
Referring to FIG. 2D to FIG. 2E, a contact 26a and interconnect 27a and 28a are formed within the contact window 26 and the metal trenches 27a, 28a, respectively. A second metal wiring is coupled with the metal wiring 21 by the contact 26a.
During etching, a high etch selectivity for the stop layer, that is, the silicon nitride layer, is required to control the thickness of the interconnects 27a and 28a. In addition, since the etch selectivity of silicon nitride is to be considered, the width of the lower part of the contact window 26a is narrower as shown in FIG. 2E. Thus, the contact resistance is increased with the reduction of contact area.